1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM) device on a semiconductor substrate and more particularly to a method of and a circuitry for a reduction of loss in a sense margin caused by capacitance coupling between bit lines of a DRAM device. Here, the sense margin Vs is defined as Vs=Vb-Vm, where Vb denotes a potential difference between a pair of bit lines, and Vs denote a minimum potential difference which can be sensed and amplified by a sense amplifier of a DRAM device.
2. Description of the Prior Art
FIG. 1 is a circuit diagram for illustrating a portion of a conventional DRAM device. This diagram shows an array of memory cells including memory capacitors 41 to 56 and transfer FETs 21 to 36 corresponding thereto, respectively. Pairs of bit lines adjacent to each other on a semiconductor substrate, namely, BL1 and BL1, BL2 and BL2, BL3 and BL3, and BL4 and BL4 are connected to sense amplifiers 1, 2, 3 and 4, respectively, so as to read and write data from and into memory cells selected by word lines WL0, WL1, WL2 and WL3, respectively. The sense amplifiers are activated by means of a signal line S. The pairs of bit lines can be equalized by means of a signal line EQ through FETs 11 to 18. During the equalizing period, a voltage Vcc/2 is applied to each bit line by means of a signal line V.sub.BL. The capacitance coupling between the bit line pairs is represented by phantom lines.
FIG. 2 is a block diagram showing a peripheral circuitry for the DRAM device of FIG. 1. An address latch 210 is provided with address signals A0 to A9. Based on the address signals, a column decoder 210 selects a bit line pair and similarly a row decoder 230 selects a word line so that a particular memory cell may be selected.
FIG. 3 is a signal waveform diagram on the respective signal lines of the DRAM device of FIG. 1. One of the bit lines of each pair which was at a ground potential GND and the other bit line of each pair which was at a voltage Vcc are equalized during a high (H) level of the equalizing signal EQ and they are reliably set at Vcc/2 by means of the signal line V.sub.BL. If the selected word line WL0 rises to the H level after the equalizing signal EQ has fallen to a low (L) level, data stored in the memory capacitors 41, 42, 43 and 44 are read out through the bit lines BL1, BL2, BL3 and BL4, respectively. If capacitance coupling between the respective bit lines can be disregarded, the bit line BLn (n being an integer) is at a potential shown by a broken line in FIG. 3. However, in a practically utilized DRAM device, an interline capacitance forms a large proportion in a parasitic capacitance of bit lines and accordingly a bit line BLn has a potential a little lower than the broken line as shown by a corresponding solid line in FIG. 3 due to a low voltage for reading an adjacent bit line BLn-1. As a result, a loss is caused in a sense margin which corresponds to a potential difference between the bit lines BLn and BLn.
Then, when the signal S for activating the sense amplifiers rises to the H level, the sense amplifiers 1, 2, 3 and 4 are activated to cause the bit lines BL1, BL2, BL3 and BL4 of a low level to be at the ground potential GND (L level) and the bit lines BL1, BL2, BL3 and BL4 of a high level to be at the potential Vcc (H level). Then, data of the memory cells related to the corresponding pairs of bit lines are read out through input/output lines (not shown). Before the selected word line WL0 falls again to the L level, the data are written again in the memory capacitors 41, 42, 43 and 44 at the ground level GND and the sense amplifier activation signal S falls again to the L level.
After that, when the equalizing signal EQ attains the H level, on bit line of each pair at the ground potential GND and the other bit line of each pair at the potential Vcc are equalized so that are reliably at the potential Vcc/2 through the signal line V.sub.BL.
Thus, the conventional DRAM device performs the reading operation and the refresh operation.
The integration scale of DRAMs is increased every year and a spacing of bit lines is decreased accordingly. Since the spacing of bit lines becomes small, a capacitance coupling between the bit lines is further increased and a loss is caused in a sense margin, resulting in an increase of a soft error ratio. The soft error is mainly caused by .alpha.-rays. When .alpha.-rays hit a semiconductor DRAM, electron and hole pairs are generated. The generated electrons are collected into bit lines due to an electric field. The thus collected electrons change the potential of the bit lines. Therefore, when the sense margin is small, soft errors may be caused at a higher ratio.